/**
 ******************************************************************************
 * @file    adc.h
 * @author  hyseim software Team
 * @date    18-Aug-2023
 * @brief   This file provides all the headers of the adc functions.
 ******************************************************************************
 * @attention
 *
 * Copyright (c) 2020 Hyseim. Co., Ltd.
 * All rights reserved.
 *
 * This software is licensed under terms that can be found in the LICENSE file
 * in the root directory of this software component.
 * If no LICENSE file comes with this software, it is provided AS-IS.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __ADC_H__
#define __ADC_H__

/* Includes ------------------------------------------------------------------*/
#include "chip_define.h"
#include "common.h"
/* Exported types ------------------------------------------------------------*/
typedef struct
{
    __IO uint32_t ADDR_AD_CSR;                  /*!< Control Register,                                  Address offset: 0x000 */                                    
    __IO uint32_t ADDR_AD_ADANS;                /*!< Ch set Register,                                   Address offset: 0x004 */                                
         uint32_t reserved0[1];                 /*!< Reserved,                                                          0x008 */                    
    __IO uint32_t ADDR_AD_CER;                  /*!< Data format Register,                              Address offset: 0x00C */
         uint32_t reserved1[1];                 /*!< Reserved,                                                          0x010 */
    __IO uint32_t ADDR_AD_SSTR;                 /*!< Simulated sampling settings Register,              Address offset: 0x014 */
         uint32_t reserved2[1];                 /*!< Reserved,                                                          0x018 */                    
    __I  uint32_t ADDR_AD_CHD_RDY;              /*!< Channel data valid Register,                       Address offset: 0x01c */
    __I  uint32_t ADDR_AD_SHADOW0;              /*!< Shadow data Register 0,                            Address offset: 0x020 */
    __I  uint32_t ADDR_AD_SHADOW1;              /*!< Shadow data Register 1,                            Address offset: 0x024 */
    __I  uint32_t ADDR_AD_DR0;                  /*!< Ch0 data Register,                                 Address offset: 0x028 */
    __I  uint32_t ADDR_AD_DR1;                  /*!< Ch1 data Register,                                 Address offset: 0x02c */
    __I  uint32_t ADDR_AD_DR2;                  /*!< Ch2 data Register,                                 Address offset: 0x030 */
    __I  uint32_t ADDR_AD_DR3;                  /*!< Ch3 data Register,                                 Address offset: 0x034 */
    __I  uint32_t ADDR_AD_DR4;                  /*!< Ch4 data Register,                                 Address offset: 0x038 */
    __I  uint32_t ADDR_AD_DR5;                  /*!< Ch5 data Register,                                 Address offset: 0x03c */
    __I  uint32_t ADDR_AD_DR6;                  /*!< Ch6 data Register,                                 Address offset: 0x040 */
    __I  uint32_t ADDR_AD_DR7;                  /*!< Ch7 data Register,                                 Address offset: 0x044 */
    __I  uint32_t ADDR_AD_DR8;                  /*!< Ch8 data Register,                                 Address offset: 0x048 */
    __I  uint32_t ADDR_AD_DR9;                  /*!< Ch9 data Register,                                 Address offset: 0x04c */
    __I  uint32_t ADDR_AD_DR10;                 /*!< Ch10 data Register,                                Address offset: 0x050 */
    __I  uint32_t ADDR_AD_DR11;                 /*!< Ch11 data Register,                                Address offset: 0x054 */
    __I  uint32_t ADDR_AD_DR12;                 /*!< Ch12 data Register,                                Address offset: 0x058 */
    __I  uint32_t ADDR_AD_DR13;                 /*!< Ch13 data Register,                                Address offset: 0x05c */
    __I  uint32_t ADDR_AD_DR14;                 /*!< Ch14 data Register,                                Address offset: 0x060 */
    __I  uint32_t ADDR_AD_DR15;                 /*!< Ch15 data Register,                                Address offset: 0x064 */
    __I  uint32_t ADDR_AD_DR16;                 /*!< Ch16 data Register,                                Address offset: 0x068 */
    __I  uint32_t ADDR_AD_DR17;                 /*!< Ch17 data Register,                                Address offset: 0x06c */
    __I  uint32_t ADDR_AD_DR18;                 /*!< Ch18 data Register,                                Address offset: 0x070 */
    __I  uint32_t ADDR_AD_DR19;                 /*!< Ch19 data Register,                                Address offset: 0x074 */
    __I  uint32_t ADDR_AD_DR20;                 /*!< Ch20 data Register,                                Address offset: 0x078 */
    __I  uint32_t ADDR_AD_DR21;                 /*!< Ch21 data Register,                                Address offset: 0x07c */
    __I  uint32_t ADDR_AD_DR22;                 /*!< Ch22 data Register,                                Address offset: 0x080 */
    __I  uint32_t ADDR_AD_DR23;                 /*!< Ch23 data Register,                                Address offset: 0x084 */
         uint32_t reserved3[7];                 /*!< Reserved,                                                  0x088 - 0x0a0 */                    
    __IO uint32_t ADDR_AD_DR31;                 /*!< TS data Register,                                  Address offset: 0x0a4 */
    __IO uint32_t ADDR_AD_PD;                   /*!< ADC power Register,                                Address offset: 0x0a8 */
    __IO uint32_t ADDR_AD_INTC;                 /*!< ADC interrupt Register,                            Address offset: 0x0ac */
    __IO uint32_t ADDR_TS_CONF0;                /*!< ADC TS Register 0,                                 Address offset: 0x0b0 */
    __IO uint32_t ADDR_TS_CONF1;                /*!< ADC TS Register 1,                                 Address offset: 0x0b4 */
    __I  uint32_t ADDR_TS_CONF2;                /*!< ADC TS Register 2,                                 Address offset: 0x0b8 */
    __IO uint32_t ADDR_AD_CLK_DIV;              /*!< ADC clk Register,                                  Address offset: 0x0bc */
    __IO uint32_t ADDR_AD_GROUP_SET_CIF1;       /*!< Group trigger source Register 1,                   Address offset: 0x0c0 */
    __IO uint32_t ADDR_AD_GROUP_SET_CIF2;       /*!< Group trigger source Register 2,                   Address offset: 0x0c4 */
    __IO uint32_t ADDR_AD_TRIGGER1_CIF;         /*!< Group 1 Ch Register 0,                             Address offset: 0x0c8 */
    __IO uint32_t ADDR_AD_TRIGGER1_CIF_EXPAND;  /*!< Group 1 Ch Register 1,                             Address offset: 0x0cc */
    __IO uint32_t ADDR_AD_TRIGGER2_CIF;         /*!< Group 2 Ch Register 0,                             Address offset: 0x0d0 */
    __IO uint32_t ADDR_AD_TRIGGER2_CIF_EXPAND;  /*!< Group 2 Ch Register 1,                             Address offset: 0x0d4 */
    __IO uint32_t ADDR_AD_TRIGGER3_CIF;         /*!< Group 3 Ch Register,                               Address offset: 0x0d8 */                        
    __IO uint32_t ADDR_AD_TRIGGER4_CIF;         /*!< Group 4 Ch Register,                               Address offset: 0x0dc */
    __IO uint32_t ADDR_AD_TRIGGER5_CIF;         /*!< Group 5 Ch Register,                               Address offset: 0x0e0 */
    __IO uint32_t ADDR_AD_DMA_D;                /*!< DMA handling Register,                             Address offset: 0x0e4 */
    __IO uint32_t ADDR_AD_RABSET_CIF;           /*!< Shadow CH set Register,                            Address offset: 0x0e8 */
} ADC_t;

typedef struct
{
    uint32_t triggerSel;                /* trigger selection */ 
    uint32_t triggerEn;                 /* trigger enable */ 
    uint32_t interruptEn;               /* conversion end interrupt enable */ 
    uint32_t channelSel;                /* channel select */ 
    uint32_t readClear;                 /* read clear data register */ 
    uint32_t diagVoltage;               /* self diagnostic voltage selection */ 
    uint32_t sampgMode;                 /* diag mode selection */ 
    uint32_t adcSampleEn;               /* single enable or disable */ 
    uint32_t dataFormat;                /* data format */ 
    uint32_t group1Trigger;             /* group 1 trigger source */ 
    uint32_t group2Trigger;             /* group 2 trigger source */
    uint32_t group3Trigger;             /* group 3 trigger source */
    uint32_t group4Trigger;             /* group 4 trigger source */
    uint32_t group5Trigger;             /* group 5 trigger source */
    uint32_t externTriggerMode;         /* External trigger mode */
    uint32_t atuTriggerMode;            /* Atu trigger mode */
    uint32_t dataPrecision;             /* data precision */ 
    uint32_t anyChannelInterruptEn;     /* Enable any single channel interrupt */
    uint32_t pdbEn;                     /* pdb enable */
    uint32_t pdbSoftEn;                 /* pdb soft enable */
    uint32_t nchSeqSample;              /* Nch mode sequence sample */
    uint32_t setPendingCh;              /* set pending sample ch */
    uint32_t pendingTrigger;            /* pending ch sample trigger */

} ADC_InitStruct_t;

typedef struct
{
    uint32_t group1Ch0;              /* group1 ch0 selection */
    uint32_t group1Ch0En;            /* group1 ch0 enable */
    uint32_t group1Ch1;              /* group1 ch1 selection */
    uint32_t group1Ch1En;            /* group1 ch1 enable */
    uint32_t group1Ch2;              /* group1 ch2 selection */
    uint32_t group1Ch2En;            /* group1 ch2 enable */
    uint32_t group1Ch3;              /* group1 ch3 selection */
    uint32_t group1Ch3En;            /* group1 ch3 enable */
    uint32_t group1Ch4;              /* group1 ch4 selection */
    uint32_t group1Ch4En;            /* group1 ch4 enable */
    uint32_t group1Ch5;              /* group1 ch5 selection */
    uint32_t group1Ch5En;            /* group1 ch5 enable */
    uint32_t group2Ch0;              /* group2 ch0 selection */
    uint32_t group2Ch0En;            /* group2 ch0 enable */
    uint32_t group2Ch1;              /* group2 ch1 selection */
    uint32_t group2Ch1En;            /* group2 ch1 enable */
    uint32_t group2Ch2;              /* group2 ch2 selection */
    uint32_t group2Ch2En;            /* group2 ch2 enable */
    uint32_t group2Ch3;              /* group2 ch3 selection */
    uint32_t group2Ch3En;            /* group2 ch3 enable */ 
    uint32_t group2Ch4;              /* group2 ch4 selection */ 
    uint32_t group2Ch4En;            /* group2 ch5 enable */
    uint32_t group2Ch5;              /* group2 ch5 selection */
    uint32_t group2Ch5En;            /* group2 ch4 enable */
    uint32_t group3Ch0;              /* group3 ch0 selection */
    uint32_t group3Ch0En;            /* group3 ch0 enable */
    uint32_t group3Ch1;              /* group3 ch1 selection */
    uint32_t group3Ch1En;            /* group3 ch1 enable */
    uint32_t group3Ch2;              /* group3 ch2 selection */
    uint32_t group3Ch2En;            /* group3 ch2 enable */
    uint32_t group3Ch3;              /* group3 ch3 selection */
    uint32_t group3Ch3En;            /* group3 ch3 enable */
    uint32_t group4Ch0;              /* group4 ch0 selection */
    uint32_t group4Ch0En;            /* group4 ch0 enable */
    uint32_t group4Ch1;              /* group4 ch1 selection */
    uint32_t group4Ch1En;            /* group4 ch1 enable */
    uint32_t group4Ch2;              /* group4 ch2 selection */ 
    uint32_t group4Ch2En;            /* group4 ch2 enable */
    uint32_t group4Ch3;              /* group4 ch3 selection */
    uint32_t group4Ch3En;            /* group4 ch3 enable */
    uint32_t group5Ch0;              /* group5 ch0 selection */
    uint32_t group5Ch0En;            /* group5 ch0 enable */
    uint32_t group5Ch1;              /* group5 ch1 selection */
    uint32_t group5Ch1En;            /* group5 ch1 enable */
    uint32_t group5Ch2;              /* group5 ch2 selection */
    uint32_t group5Ch2En;            /* group5 ch2 enable */
    uint32_t group5Ch3;              /* group5 ch3 selection */
    uint32_t group5Ch3En;            /* group5 ch3 enable */
}ADC_NchConfigStruct_t;

typedef struct
{
    uint32_t tsOverflowIrq;          /* Temperature overflow interrupt enable */
    uint32_t tsUnderflowIrq;         /* Temperature overflow interrupt enable */
    uint32_t tsIrq;                  /* Temperature sampling interrupt enable */
}ADC_TsConfigStruct_t;

typedef struct
{
    uint32_t dmaReq;                 /* DMA handling selection */
    uint32_t interruptReq;           /* Interrupt selection */
    uint32_t errorInterruptReq;      /* Operation error interrupt enable */
    uint32_t chFinsh;                /* Number of request channels since completion of sampling */
}ADC_InterruptConfig_t;

typedef struct
{
    uint32_t tmux;                   /* The number of delay cycles from CS signal to sampling start */
    uint32_t thold;                  /* Number of sampling cycles required */
    uint32_t tgap;                   /* Simulate the number of cycles required for ADC conversion */
    uint32_t tde;                    /* Number of cycles between the end of conversion and the start of next sampling */
}ADC_SampleTime_t;



/* Exported macro ------------------------------------------------------------*/
#define ADC0       ((ADC_t*)(ADC0_BASE))  
#define ADC1       ((ADC_t*)(ADC1_BASE)) 

/* Exported constants --------------------------------------------------------*/
/* Trigger source from ATU to ADC */
enum
{
    TRIGGER_SOURCE_EXTERNAL = 0,
    TRIGGER_SOURCE_TRGA0N = 1,
    TRIGGER_SOURCE_TRGA1N = 2,
    TRIGGER_SOURCE_TRGA2N = 3,
    TRIGGER_SOURCE_TRGA3N = 4,
    TRIGGER_SOURCE_TRGA4N = 5,
    TRIGGER_SOURCE_TRGA6N = 6,
    TRIGGER_SOURCE_TRGA7N = 7,
    TRIGGER_SOURCE_TRG0N = 8,
    TRIGGER_SOURCE_TRG4AN = 9,
    TRIGGER_SOURCE_TRG4BN = 10,
    TRIGGER_SOURCE_TRG4AN_TRG4BN = 11,
    TRIGGER_SOURCE_TRG4ABN = 12,
    TRIGGER_SOURCE_TRG7AN = 13,
    TRIGGER_SOURCE_TRG7BN = 14,
    TRIGGER_SOURCE_TRG7AN_TRG7BN = 15,
    TRIGGER_SOURCE_TRG7ABN = 16,
    TRIGGER_SOURCE_SOFT = 17,
};

enum
{
    CH0 = 0,
    CH1 = 1,
    CH2 = 2,
    CH3 = 3,
    CH4 = 4,
    CH5 = 5,
    CH6 = 6,
    CH7 = 7,
    CH8 = 8,
    CH9 = 9,
    CH10 = 10,
    CH11 = 11,
    CH12 = 12,
    CH13 = 13,
    CH14 = 14,
    CH15 = 15,
    CH16 = 16,
    CH17 = 17,
    CH18 = 18,
    CH19 = 19,
    CH20 = 20,
    CH21 = 21,
    CH22 = 22,
    CH23 = 23,
};

/******************************    Bit definition for ADC_CSR register  *******************************/
#define EXTR_TRIGGER_ENABLE                         (0x1U << 0)         /*!< ADC External trigger enable */
#define ATU_TRIGGER_ENABLE                          (0x1U << 1)         /*!< ADC ATU trigger enable */
#define INTERRUPT_ENABLE                            (0x1U << 4)         /*!< ADC Interrupt enable */
#define SINGLE_MODE                                 (0x0U << 5)         /*!< ADC Single mode set */
#define ONECYCLE_MODE                               (0x1U << 5)         /*!< ADC Onecycle mode set */
#define CONTINUE_MODE                               (0x2U << 5)         /*!< ADC Continue mode set */
#define NCH_MODE                                    (0x3U << 5)         /*!< ADC Nch mode set */
#define PDB_ENABLE                                  (0x1U << 8)         /*!< ADC and PDB share enable */
#define PDB_B2B_SOFT                                (0x1U << 9)         /*!< ADC and PDB B2B soft mode */
#define GROUP_SEQ_ENABLE                            (0x1U << 15)        /*!< ADC NCh mode, Group sequence sample enable */
#define SOFT_START_SAMPLE                           (0x1U << 23)        /*!< ADC soft start sample */
#define BREAK_SAMPLE                                (0x0U << 31)        /*!< ADC sample breaked */
/******************************    Bit definition for ADC_CER register  *******************************/
#define DATA_WIDTH_8                                (0x2U << 17)        /*!< ADC sampling data 8-bit */
#define DATA_WIDTH_10                               (0x1U << 17)        /*!< ADC sampling data 10 bits */
#define DATA_WIDTH_12                               (0x0U << 17)        /*!< ADC sampling data 12 bits */
#define READ_CLEAR_ENABLE                           (0x1U << 21)        /*!< After reading data, clear the data register */        
#define ANY_SINGLE_INTERRUPT_ENABLE                 (0x1U << 30)        /*!< Interrupt at the end of any channel */
#define DATA_TO_RIGHT                               (0x0U << 31)        /*!< Right data format */ 
#define DATA_TO_LEFT                                (0x1U << 31)        /*!< Left data format */ 
/******************************    Bit definition for ADC_INTC register  *******************************/
#define TRIGGER_CLASH_INTERRUPT_ENABLE              (0x1U << 6)         /*!< Sampling conflict interrupt enable */ 
#define DMA_CLASH_INTERRUPT_ENABLE                  (0x1U << 7)         /*!< DMA handling conflict interrupt enable */ 
#define SINGLE_INTERRUPT_ENABLE                     (0x1U << 16)        /*!< Single mode sampling completion interrupt enable */ 
#define ONECYCLE_INTERRUPT_ENABLE                   (0x1U << 17)        /*!< Onecycle mode sampling completion interrupt enable */ 
#define CONTINUE_INTERRUPT_ENABLE                   (0x1U << 18)        /*!< Continue mode sampling completion interrupt enable */ 
#define NCH_INTERRUPT_ENABLE                        (0x1U << 19)        /*!< Continue mode sampling completion interrupt enable */ 
#define NCH_ALL_FINISH_INTERRUPT_ENABLE             (0x1U << 20)        /*!< Nch mode all group sampling completion interrupt enable */ 
#define ANY_CH_FINISH_INTERRUPT_ENABLE              (0x1U << 21)        /*!< Enable interrupt completion for sampling any number of channels */ 
#define EACH_CH_FINISH_DMA_REQ                      (0x1U << 24)        /*!< Starting DMA request for each channel completed by sampling */ 
#define ONECYCLE_DMA_REQ                            (0x1U << 25)        /*!< Onecycle mode sampling completes DMA requests */ 
#define CONTINUE_DMA_REQ                            (0x1U << 26)        /*!< Continue mode sampling completion starts DMA request */ 
#define NCH_DMA_REQ                                 (0x1U << 27)        /*!< Nch mode sampling completed DMA request */ 
#define NCH_ALL_FINISH_DMA_REQ                      (0x1U << 28)        /*!< Starting DMA request after all group sampling in Nch mode is completed */ 
#define ANY_CH_FINISH_DMA_REQ                       (0x1U << 29)        /*!< Sample any number of channels to complete DMA requests */ 
/******************************    Bit definition for ADC_TSCON0 register  *******************************/
#define TS_INTERRUPT_ENABLE                         (0x1U << 18)        /*!< Temperature sampling completion interrupt enable */
#define TS_UNDERFLOW_INTERRUPT_ENABLE               (0x1U << 19)        /*!< Temperature overflow interrupt enable */
#define TS_OVERFLOW_INTERRUPT_ENABLE                (0x1U << 20)        /*!< Temperature overflow interrupt enable */
/******************************    Bit definition for ADC_CLKDIV register  *******************************/
#define CLK_DIV_                            (0x1U << 8)         /*!<  */
//div clk ????????



/* Exported functions ------------------------------------------------------- */
void ADC_Init(ADC_t* ADCx, ADC_InitStruct_t* ADC_InitStruct);
void ADC_NchCofig(ADC_t* ADCx, ADC_NchConfigStruct_t* ADC_NchConfigStruct);
void ADC_SetCh(ADC_t* ADCx, uint32_t startCh, uint32_t stopCh);
void ADC_Cmd(ADC_t* ADCx, FunctionalState_t NewState);
void ADC_TsIrqEn(ADC_t* ADCx, ADC_TsConfigStruct_t* ADC_TsConfigStruct);
void ADC_TsOverflowValue(ADC_t* ADCx, uint16_t overflowValue);
void ADC_TsUnderflowValue(ADC_t* ADCx, uint16_t underflowValue);
void ADC_Shadow0Config(ADC_t* ADCx, FunctionalState_t NewState, uint32_t setCh);
void ADC_Shadow1Config(ADC_t* ADCx, FunctionalState_t NewState, uint32_t setCh);
void ADC_ClkDiv(ADC_t* ADCx, uint32_t divFactor);
void ADC_InterruptConfig(ADC_t* ADCx, ADC_InterruptConfig_t* ADC_InterruptConfig);
void ADC_SoftStartSample(ADC_t* ADCx, FunctionalState_t NewState);
void ADC_SampleTimeSet(ADC_t* ADCx, ADC_SampleTime_t* SampleTime);
void ADC_InterruptClear(ADC_t* ADCx);

#endif
/*******************(C)COPYRIGHT 2020 Hyseim ***********END OF FILE************/
